In the architecture of computer systems, a major module is the memory system which works in conjunction with the processor and which memory system holds and supplies the data and instructions necessary to the operation of the system. One such type of memory system involves the use of PROM memory modules which involve programmable read only memory units which are generally used to hold "fixed" data for use of the computer system.
The information stored in the PROM memory is critical to the integrity of system operation and such system operation can run amok should the data from the PROM memory be corrupted or altered.
Such memory units are also made up of ROM modules which involve read-only memory and which also hold significant "fixed" data.
Examples of important and significant data which may reside in a PROM or a ROM memory system are such items as:
(i) low level "bootstrap" (start-up) program code which is used to initialize a system;
(ii) specialized and unique information for system identification and configuration functions;
(iii) data integrity value information such as encryption or decryption keys.
The integrity of the ROM/PROM memory data is especially critical since a system may not yet be sufficiently initialized (up) enough at the period of initialization before other higher and more sophisticated levels of error detection are functioning operationally.
The generally common method of error detection in memory systems, whether RAMs (random access memories) or ROMs/PROMs, is the use of the "parity" data system. Parity is a method whereby "extra" data bits are stored along with the real data bits. These extra bits, called "parity bits", contain a value that is based upon the value of the actual data package under consideration. At such time as the data information is read out from memory, the parity bits are read out as well.
The parity value of the "actual data read out" is recalculated from the real data bits (via a parity logic circuit) and the calculated parity value is then compared to the parity bit or bits read out from the parity memory. If these two values are equal, then there is a high probability that the actual data read-out is valid and free from errors that may have been induced during the writing-in, the storage of, and the reading-out of the data in the memory subsystem.
In the physical hardware implementation of a parity checking system for memory, several factors are extant:
(a) extra storage elements (PROM chips) are required to store the parity bit(s);
(b) a means of collecting and checking out the parity bits must be added to the system.
One example of a parity check system is shown in U.S. Pat. No. 4,809,279 which is commonly assigned to the same ownership as this instant application. This type system is limited to only one type of parity operation (odd. parity) while the instant application provides a choice factor for using odd or even parity.
In the present day commercial marketplace, standard parity-checking integrated circuit chips (IC's) are available. These devices use one parity bit for each eight bits of information (data). Thus it can be realized that one bit of extra memory must be added to the system for each eight bits (data) of system memory width. Now since most functioning practical systems have requirements for memory much wider than eight bits, this can lead to problems involving additional cost consideration and space requirements in the system.
Another complication to the use of parity systems in PROM memory structures is that standard industry PROM chips are usually made eight bits wide in configuration. Even if it were possible to find a one-bit wide PROM, there is still the consideration that it is highly desirable to build a memory structure using only "one type" of memory chip rather than a mixture of different types of chips.
Because of this impracticability, it would appear that few systems use data integrity schemes for PROM memory data. Thus the architectural arrangement presented in this disclosure provides a means for reducing the costs of parity schemes in PROM memory systems and permits uniformity of PROM module units and, most importantly, permits means for insuring the integrity of the system by permitting the detection of data corruption errors in the PROM memory banks. Because of the use of fewer memory chips and the uniformity of using the same type of memory chips, it is possible to provide considerable efficiencies in operation and cost reduction.